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OR for Electronic design

Marc Sevaux presented his latest work on Hardware architectures for optimization at ROADEF 2013

One of the latest work of the OR-Group concerns the design of hardware archtectures for solving optimization problems. The goal of this project is to create a specific hardware equipement dedicated to solving optimization problems. It has been shown extremely powerful and faster than GP-GPU implementation.

Slides can be downloaded by clicking here.

OR-Group gave a seminar at the University of Hamburg

On January 20, 2011, Marc Sevaux had given a seminar at the University of Hamburg. Professor Stefan Voß had invited us to present  our activities in optimization conducted at Lab-STICC. The people attended the presentation did not expect to see how many optimization problems you can encounter in electronic design. The discussion that follows was fruitful and give us a new path for potential collaboration.

Invited seminar at CEA

The OR-Group has been invited on 1st of december 2010 at the CEA (Commissariat à l'énergie atomique) to present its activites in optimization for electronic design and create potential collaborations in the future. The presentation was about 2h and raised a large number of questions and an active discussion around potential common subjects. CEA is hosting several former PhD students of the Lab-STICC, including Kods Trabelsi, a former member of our team.

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