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Rachid Dafali defended his PhD

On May 30, Rachid Dafali defended his PhD Thesis in front of a jury composed by two external referees, two external examiners and the two co-advisors. After a presentation of 45 minutes, the jury asked him a number of questions for which Rachid Dafali answered correctly. After a short deliberation, the jury unanimously decided to grant Mr. Dafali with the PhD diploma (Grade de Docteur, in French).

Abstract: This work addresses the issue of communications between processing or storage units within reconfigurable system on chip. Our approach relies on the implementation of reconfiguration mechanisms in Network On Chips (NoC) in order to solve the increasing problem of traffic variability in future RSoC. Thus, the objective is to provide the NoC with self-adaptitvity properties so that it can adapt at run-time to real and variable communication requirements of processing and storage units. This thesis proposes two original and efficient mechanisms of reconfiguration. The first one relies on the concept of dynamically reconfigurable memory buffers that allow for the runtime adaptation of FIFO depths in Network Interfaces according to communication needs. The second one is complementary and controls the TDMA table which is dynamically reconfigurable, it can adapt the number of time slots allocated to different communications according to real bandwidth needs while preserving guaranteed traffic property. This work also consists in developing a new CAD environment, $\mu$Spider II, to automize the design flow. This framework is composed of various associated tools that perform exploration, optimization and VHDL code generation, it also provides material for test and performances evaluation. Both approaches have been validated with experiments and implementations on FPGA with different versions of the $\mu$Spider II NoC with multiprocessor architectures.

You can access the presentation here.

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