High Level Synthesis (HLS) is one of the central problem in automatic design of electronic circuits. Considering the current state-of-the-art methods for automated integrated circuit design, new solutions for the design flow should be proposed to reply to the fast growth of the digital technology and the reduced time-to-market that companies have to follow. High level synthesis tools appear to bridge the gap between modeling architectures and the actual achievement of the integrated circuit. Nevertheless, it is necessary to go further.
In the design flow (see picture below), four main problem can be tackled by optimization techniques: the selection problem, the allocation problem, the scheduling problem and the assignment problem. All of them are largely intricated and should be considered in an unified approach.
New approaches have been proposed to explore the solution space from simple descent method up to GRASP and VNS methods in order to minimize the surface of component at the end of the electronic design of a circuit (dedicated to a specific application).